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Current group: comp.arch
Question about sdram DIMM, module bank, component bank, page size
| ghh | | David Wang | | Yogesh | | ghh | | David Wang | | MitchAlsup at aol.com |
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| | From: | ghh | | Subject: | Question about sdram DIMM, module bank, component bank, page size | | Date: | 14 Jan 2005 03:26:52 -0800 |
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 | Greetings folks,
I am just a dumb managerial type trying to improve my technical
knowledge so please bear with my basic questions.
So in my line of work, I hear terms like so-and-so motherboard supports
x-megabytes of sdram memory. Now, that's easy to understand, 128 MB of
sdram max. Okay, got it. Then, comes the disclaimers like "by the way,
the processor can only handle up to 4 module banks of sdram". The
jargon that catches me there is the "module banks". Then comes the
piling on by which time, my eyes are not just glazed over, they're
completely frosted: "And of course, each module bank will support only
either 2 or 4 component banks". I hear other things like DIMM page size
which I gather is different to the processor settable page size used in
virtual memory. Given the looks that I see, even from some of the
engineers, I gather this stuff isn't common knowledge.
Okay, so the jargon list that I'm trying to understand is:
1. module bank
2. component bank
3. page size when used in the context of SDRAM DIMMs
I've tried googling but I've had very little improvement in
understanding even after reading Stokes and even paging through
Patterson&Hennessey.
I realize that there is variation when you involve DDR and RDRAM. So to
make things simple for a simpleton like me, I hope anyone who cares to
elaborate on this topic will limit it to just plain old SDRAM DIMMs.
Any and all pointers to descriptions and explainations of the above
would be truly welcome.
Oh, and usage of real-life examples like so-and-so ram chip has this
and so-and-so processor has that are fine. I'm happy to google the
datasheets and try and figure it out.
\GHH
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| | From: | David Wang | | Subject: | Re: Question about sdram DIMM, module bank, component bank, page size | | Date: | Fri, 14 Jan 2005 17:31:57 +0000 (UTC) |
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| ghh wrote:
> So in my line of work, I hear terms like so-and-so motherboard supports
> x-megabytes of sdram memory. Now, that's easy to understand, 128 MB of
> sdram max. Okay, got it. Then, comes the disclaimers like "by the way,
> the processor can only handle up to 4 module banks of sdram". The
The processor doesn't know anything about DRAM, much less how many of
them there are. It talkes to the DRAM controller that can handle a
certain number of ranks (your terminology of module banks), rows,
columns etc.
> jargon that catches me there is the "module banks". Then comes the
> piling on by which time, my eyes are not just glazed over, they're
> completely frosted: "And of course, each module bank will support only
> either 2 or 4 component banks". I hear other things like DIMM page size
> which I gather is different to the processor settable page size used in
> virtual memory. Given the looks that I see, even from some of the
> engineers, I gather this stuff isn't common knowledge.
It is "common knowledge"... To people who design this stuff... :)
It's not a difficult thing to comprehend, but it is complex because
there's a lot of esoteric stuff in there, and most of it isn't
important to anyone except those that deal with DRAMs and DRAM
controller designs, so it's hard to find a good reference on all
of this stuff.
> Okay, so the jargon list that I'm trying to understand is:
> 1. module bank
A number of DRAM devices are tied together in parallel to respond
to a given command. This is also knowns as a "rank" of devices.
A memory module typically has one or two ranks of devices on it.
> 2. component bank
Modern DRAM devices are internally multi-banked, so while one bank
is precharging or accessing a row, another bank can be accessed
concurrently.
> 3. page size when used in the context of SDRAM DIMMs
Depending on the DRAM device and the organization of those devices
into a rank of memory.
For example, if I use a 256 Mbit SDRAM device, each device is a x16
wide device, and the device is organized into 4 bank internally, each
bank consists of 8192 rows, and each row has 512 columns. Then, I can
take 4 of these devices and make a 128 MB module out of it.
Each time I access a row on this memory module, that is essentially a
"DRAM page", and that page size is 512 (columns) x 64 (bits per column).
So my page size here is 4 KB.
Unfortunately, I can use different densities of DRAM devices with
different x4, x8 and x16 data bus widths to configure a 128 MB DRAM
module, and for those different configurations of DRAM modules, the
size of a "DRAM page" may be different.
> I've tried googling but I've had very little improvement in
> understanding even after reading Stokes and even paging through
> Patterson&Hennessey.
This stuff isn't in H&P. There should be a book out in 2006 that
will cover all this stuff though. ;)
> I realize that there is variation when you involve DDR and RDRAM. So to
> make things simple for a simpleton like me, I hope anyone who cares to
> elaborate on this topic will limit it to just plain old SDRAM DIMMs.
> Any and all pointers to descriptions and explainations of the above
> would be truly welcome.
> Oh, and usage of real-life examples like so-and-so ram chip has this
> and so-and-so processor has that are fine. I'm happy to google the
> datasheets and try and figure it out.
HTH.
--
davewang202(at)yahoo(dot)com
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| | From: | Yogesh | | Subject: | Re: Question about sdram DIMM, module bank, component bank, page size | | Date: | 15 Jan 2005 10:35:42 -0800 |
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| may be you should look at:
http://arstechnica.com/paedia/r/ram_guide/ram_guide.part1-2.html
it gives a detailed description of all aspects dram devices..very good
for beginners..
Yogesh
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| | From: | ghh | | Subject: | Re: Question about sdram DIMM, module bank, component bank, page size | | Date: | 17 Jan 2005 01:05:11 -0800 |
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| David,
Your explaination was excellent. Thanks! I'm much further along the
road to understanding.
However, after further reading, I am missing out how to find out how
many rows and columns a particular device has.
Let's say, "fictionally" :-), a board vendor comes to me saying, buy
our board, it's got 4 pieces of AMIC A43L3616 SDRAM, that's 4 devices,
and each are 2Mx16bitx4banks.
Thus, first of all, I believe that comes out to 64MB of SDRAM.
The sdram data sheet says "DRAM organized as 4 x 2,097,152" but doesn't
tell me how many rows/columns it has. Can this be calculated based on
the fact that there are x number of row address lines?
Thanks,
\ghh
David Wang wrote:
> ghh wrote:
>
> > So in my line of work, I hear terms like so-and-so motherboard
supports
> > x-megabytes of sdram memory. Now, that's easy to understand, 128 MB
of
> > sdram max. Okay, got it. Then, comes the disclaimers like "by the
way,
> > the processor can only handle up to 4 module banks of sdram". The
>
> The processor doesn't know anything about DRAM, much less how many of
> them there are. It talkes to the DRAM controller that can handle a
> certain number of ranks (your terminology of module banks), rows,
> columns etc.
>
> > jargon that catches me there is the "module banks". Then comes the
> > piling on by which time, my eyes are not just glazed over, they're
> > completely frosted: "And of course, each module bank will support
only
> > either 2 or 4 component banks". I hear other things like DIMM page
size
> > which I gather is different to the processor settable page size
used in
> > virtual memory. Given the looks that I see, even from some of the
> > engineers, I gather this stuff isn't common knowledge.
>
> It is "common knowledge"... To people who design this stuff... :)
>
> It's not a difficult thing to comprehend, but it is complex because
> there's a lot of esoteric stuff in there, and most of it isn't
> important to anyone except those that deal with DRAMs and DRAM
> controller designs, so it's hard to find a good reference on all
> of this stuff.
>
> > Okay, so the jargon list that I'm trying to understand is:
> > 1. module bank
>
> A number of DRAM devices are tied together in parallel to respond
> to a given command. This is also knowns as a "rank" of devices.
> A memory module typically has one or two ranks of devices on it.
>
> > 2. component bank
>
> Modern DRAM devices are internally multi-banked, so while one bank
> is precharging or accessing a row, another bank can be accessed
> concurrently.
>
> > 3. page size when used in the context of SDRAM DIMMs
>
> Depending on the DRAM device and the organization of those devices
> into a rank of memory.
>
> For example, if I use a 256 Mbit SDRAM device, each device is a x16
> wide device, and the device is organized into 4 bank internally, each
> bank consists of 8192 rows, and each row has 512 columns. Then, I can
> take 4 of these devices and make a 128 MB module out of it.
>
> Each time I access a row on this memory module, that is essentially a
> "DRAM page", and that page size is 512 (columns) x 64 (bits per
column).
> So my page size here is 4 KB.
>
> Unfortunately, I can use different densities of DRAM devices with
> different x4, x8 and x16 data bus widths to configure a 128 MB DRAM
> module, and for those different configurations of DRAM modules, the
> size of a "DRAM page" may be different.
>
> > I've tried googling but I've had very little improvement in
> > understanding even after reading Stokes and even paging through
> > Patterson&Hennessey.
>
> This stuff isn't in H&P. There should be a book out in 2006 that
> will cover all this stuff though. ;)
>
> > I realize that there is variation when you involve DDR and RDRAM.
So to
> > make things simple for a simpleton like me, I hope anyone who cares
to
> > elaborate on this topic will limit it to just plain old SDRAM
DIMMs.
> > Any and all pointers to descriptions and explainations of the above
> > would be truly welcome.
>
> > Oh, and usage of real-life examples like so-and-so ram chip has
this
> > and so-and-so processor has that are fine. I'm happy to google the
> > datasheets and try and figure it out.
>
> HTH.
>
>
>
> --
> davewang202(at)yahoo(dot)com
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| | From: | David Wang | | Subject: | Re: Question about sdram DIMM, module bank, component bank, page size | | Date: | Mon, 17 Jan 2005 18:29:02 +0000 (UTC) |
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| ghh wrote:
> David,
> Your explaination was excellent. Thanks! I'm much further along the
> road to understanding.
> However, after further reading, I am missing out how to find out how
> many rows and columns a particular device has.
> Let's say, "fictionally" :-), a board vendor comes to me saying, buy
> our board, it's got 4 pieces of AMIC A43L3616 SDRAM, that's 4 devices,
> and each are 2Mx16bitx4banks.
> Thus, first of all, I believe that comes out to 64MB of SDRAM.
> The sdram data sheet says "DRAM organized as 4 x 2,097,152" but doesn't
> tell me how many rows/columns it has. Can this be calculated based on
> the fact that there are x number of row address lines?
The data should be on the DRAM device datasheet
somewhere. For example, take the 1 Gbit DDR2 SDRAM
datasheet from Micron:
http://download.micron.com/pdf/datasheets/dram/ddr2/1GbDDR2.pdf
The configuration table tells you that the 1 Gbit DDR2
device can be configured as 256 Meg x4, 128 Meg x8 or
64 Meg x16. The table also tells you that internally,
the 1 Gbit DDR2 SDRAM device is configured as 8 banks
of 16384 rows with 2048 columns per row, 8 banks of
16384 rows with 1024 columns per row, or 8 banks of
8192 rows with 1024 columns per row, respectively.
Just find the correct configuration and multiply out
the number of columns by the width of a column (8
bytes per DIMM), and that's your "DRAM page size".
--
davewang202(at)yahoo(dot)com
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| | From: | MitchAlsup at aol.com | | Subject: | Re: Question about sdram DIMM, module bank, component bank, page size | | Date: | 14 Jan 2005 09:16:33 -0800 |
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| First there are DIMMs which plug into the motherboard. Most
motherboards allow (3 or) 4 DIMMs to be inserted. These DIMMs carry the
DRAM chips. These DIMMs provide a 64-bit (sometimes plus ECC) data path
to and from the DRAM controller and an address/command bus from the
DRAM controller to the DRAM chips.Sometimes there is an address/command
buffer/register/latch used to electrically isolate the heavy electrical
load of the DRAM address and command wires from the bus the DIMMs plug
into.
Second, a DIMM can have one or two Ranks of DRAM chips. A Rank of DRAM
chips all respond to a specific part of the physical address space. A
DIMM with 2 Ranks looks (almost) like a DIMM with a single Rank as far
as data bus electrical loading goes. So, if the manufacture can fit all
the DRAM chips on the DIMM, the user gets more memory capacity.
Third, a DDR-II DRAM chip can have either 4 internal banks or 8
internal banks (>1 GBit). Each command to a Rank operates on a single
Bank and operates every DRAM chip associated with that Rank, and
several Banks can be in various stages of operation at any point in
time.
As seen by the DRAM controller, a fully populated DRAM system can have
as many as (DIMMs*RANKs*Banks) = 4*2*8 = 64 Banks; however, most
controllers only keep track of only 16 (or fewer) banks.
I suggest that you google for DDR-II DRAM and see if you can find a
datasheet *.pdf for both the DIMM and for the DRAM chips upon the DIMM.
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