 | | From: | Paul A. Clayton | | Subject: | Low power benefits | | Date: | 12 Jan 2005 17:15:23 GMT |
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 | Some of the benefits of lower power processor designs are not
commonly presented. Although the benefits of less cooling noise
for personal computers, of longer battery life for portable
computers, and of lower electricity costs and greater compute
density for rackmounted servers are presented, slightly more
subtle benefits are less commonly presented.
Lower power systems have an effect on RAS through several
mechanisms. Reducing heat stresses tends to increase
reliability. Reducing the complexity/'volume' of cooling tends
to increase reliability. Reducing dependence on active cooling
tends to increase availability (i.e., a lower power system can
maintain a higher proportion of peak performance when active
cooling fails). The tendency to reduce power use by using a
smaller processor also allows greater integration which tends to
increase reliability (at the cost of serviceability [though
having larger field-replacable-units has some advantages]). The
reduction in typical power use tends to increase availability by
allowing a fixed size/weight of back-up batteries to supply
sufficient power for a longer period of time.
Lower power systems can also make a given quality of compute
power practical given certain limits of a location (whether
cooling systems or electrical systems [and upgrading such systems
can be expensive and can temporarily reduce availability {cut-off
of cooling or electrical service is more likely both during
installation and a 'debugging' period; electrical fires are
probably slightly more likely during or immediately after an
electrical upgrade; and network cabling can be damaged during
installations}]).
A lower power processor might also allow more pins to be used for
off-chip communication because fewer pins are necessary for power
and ground.
Lower power processors also tend to have shorted pipelines,
reducing the cost of branch mispredictions (which would improve
performance for some common server code).
Nick (and other sysadmins) probably have other reasons why
Watts/MI can be important.
Paul A. Clayton
(a 'Dysthymicdolt' reachable at aol.com)
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| | From: | Eugene Nalimov | | Subject: | Re: Low power benefits | | Date: | Wed, 12 Jan 2005 13:25:13 -0800 |
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| "Paul A. Clayton" wrote in message
news:20050112121523.13916.00000010@mb-m04.aol.com...
>...
> Lower power processors also tend to have shorted pipelines,
> reducing the cost of branch mispredictions (which would improve
> performance for some common server code).
VIA C3: 16 pipeline stages (20W @ 1.3GHz).
Itanium2: 8 pipeline stages (62W @ 1.3GHz)
Thanks,
Eugene
> Nick (and other sysadmins) probably have other reasons why
> Watts/MI can be important.
>
>
> Paul A. Clayton
> (a 'Dysthymicdolt' reachable at aol.com)
>
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| | From: | Niels_Jørgen_Kruse | | Subject: | Re: Low power benefits | | Date: | Thu, 13 Jan 2005 14:38:14 +0100 |
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| Eugene Nalimov wrote:
> "Paul A. Clayton" wrote in message
> news:20050112121523.13916.00000010@mb-m04.aol.com...
> >...
> > Lower power processors also tend to have shorted pipelines,
> > reducing the cost of branch mispredictions (which would improve
> > performance for some common server code).
>
> VIA C3: 16 pipeline stages (20W @ 1.3GHz).
> Itanium2: 8 pipeline stages (62W @ 1.3GHz)
PPC7447A: 7 pipeline stages (18.3W @ 1.3GHz)
(You are talking "typical" power?)
The C3 pipeline length is unusual. What is the fetch-execute latency?
Sometimes pipeline lengths are inflated by counting cache access.
--
Mvh./Regards, Niels Jørgen Kruse, Vanløse, Denmark
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| | From: | Eugene Nalimov | | Subject: | Re: Low power benefits | | Date: | Thu, 13 Jan 2005 09:33:17 -0800 |
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| ""Niels Jørgen Kruse"" wrote in message
news:1gqc07f.1d6nin11tgdsb6N%nospam@ab-katrinedal.dk...
> Eugene Nalimov wrote:
>
>> "Paul A. Clayton" wrote in message
>> news:20050112121523.13916.00000010@mb-m04.aol.com...
>> >...
>> > Lower power processors also tend to have shorted pipelines,
>> > reducing the cost of branch mispredictions (which would improve
>> > performance for some common server code).
>>
>> VIA C3: 16 pipeline stages (20W @ 1.3GHz).
>> Itanium2: 8 pipeline stages (62W @ 1.3GHz)
> PPC7447A: 7 pipeline stages (18.3W @ 1.3GHz)
>
> (You are talking "typical" power?)
No, I gave worst case power numbers for Itanium2 and VIA.
See http://www.via.com.tw/en/products/processors/c3/ and
http://www.intel.com/design/itanium/itanium/Itanium2ProdBrief.pdf.
Thanks,
Eugene
> The C3 pipeline length is unusual. What is the fetch-execute latency?
> Sometimes pipeline lengths are inflated by counting cache access.
>
> --
> Mvh./Regards, Niels Jørgen Kruse, Vanløse, Denmark
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| | From: | CJT | | Subject: | Re: Low power benefits | | Date: | Thu, 13 Jan 2005 17:39:47 GMT |
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| Eugene Nalimov wrote:
> ""Niels Jørgen Kruse"" wrote in message
> news:1gqc07f.1d6nin11tgdsb6N%nospam@ab-katrinedal.dk...
>
>>Eugene Nalimov wrote:
>>
>>
>>>"Paul A. Clayton" wrote in message
>>>news:20050112121523.13916.00000010@mb-m04.aol.com...
>>>
>>>>...
>>>>Lower power processors also tend to have shorted pipelines,
>>>>reducing the cost of branch mispredictions (which would improve
>>>>performance for some common server code).
>>>
>>>VIA C3: 16 pipeline stages (20W @ 1.3GHz).
>>>Itanium2: 8 pipeline stages (62W @ 1.3GHz)
>>
>>PPC7447A: 7 pipeline stages (18.3W @ 1.3GHz)
>>
>>(You are talking "typical" power?)
>
>
> No, I gave worst case power numbers for Itanium2 and VIA.
> See http://www.via.com.tw/en/products/processors/c3/ and
> http://www.intel.com/design/itanium/itanium/Itanium2ProdBrief.pdf.
I don't see where in that marketing brochure it says the itanium
numbers are "worst case."
>
> Thanks,
> Eugene
>
>
>>The C3 pipeline length is unusual. What is the fetch-execute latency?
>>Sometimes pipeline lengths are inflated by counting cache access.
>>
>>--
>>Mvh./Regards, Niels Jørgen Kruse, Vanløse, Denmark
>
>
>
--
The e-mail address in our reply-to line is reversed in an attempt to
minimize spam. Our true address is of the form che...@prodigy.net.
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| | From: | CJT | | Subject: | Re: Low power benefits | | Date: | Thu, 13 Jan 2005 17:44:45 GMT |
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| CJT wrote:
> Eugene Nalimov wrote:
>
>> ""Niels Jørgen Kruse"" wrote in message
>> news:1gqc07f.1d6nin11tgdsb6N%nospam@ab-katrinedal.dk...
>>
>>> Eugene Nalimov wrote:
>>>
>>>
>>>> "Paul A. Clayton" wrote in message
>>>> news:20050112121523.13916.00000010@mb-m04.aol.com...
>>>>
>>>>> ...
>>>>> Lower power processors also tend to have shorted pipelines,
>>>>> reducing the cost of branch mispredictions (which would improve
>>>>> performance for some common server code).
>>>>
>>>>
>>>> VIA C3: 16 pipeline stages (20W @ 1.3GHz).
>>>> Itanium2: 8 pipeline stages (62W @ 1.3GHz)
>>>
>>>
>>> PPC7447A: 7 pipeline stages (18.3W @ 1.3GHz)
>>>
>>> (You are talking "typical" power?)
>>
>>
>>
>> No, I gave worst case power numbers for Itanium2 and VIA.
>> See http://www.via.com.tw/en/products/processors/c3/ and
>> http://www.intel.com/design/itanium/itanium/Itanium2ProdBrief.pdf.
>
>
> I don't see where in that marketing brochure it says the itanium
> numbers are "worst case."
This might be relevant:
http://www.dac.com/40th/40acceptedpapers.nsf/0/1144346099a98f9487256dc60058c453/$FILE/41_3.PDF
>
>>
>> Thanks,
>> Eugene
>>
>>
>>> The C3 pipeline length is unusual. What is the fetch-execute latency?
>>> Sometimes pipeline lengths are inflated by counting cache access.
>>>
>>> --
>>> Mvh./Regards, Niels Jørgen Kruse, Vanløse, Denmark
>>
>>
>>
>>
>
>
--
The e-mail address in our reply-to line is reversed in an attempt to
minimize spam. Our true address is of the form che...@prodigy.net.
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| | From: | Eugene Nalimov | | Subject: | Re: Low power benefits | | Date: | Thu, 13 Jan 2005 11:29:11 -0800 |
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| "CJT" wrote in message
news:41E6B264.2090305@prodigy.net...
> Eugene Nalimov wrote:
>> ""Niels Jørgen Kruse"" wrote in message
>> news:1gqc07f.1d6nin11tgdsb6N%nospam@ab-katrinedal.dk...
>>
>>>Eugene Nalimov wrote:
>>>
>>>
>>>>"Paul A. Clayton" wrote in message
>>>>news:20050112121523.13916.00000010@mb-m04.aol.com...
>>>>
>>>>>...
>>>>>Lower power processors also tend to have shorted pipelines,
>>>>>reducing the cost of branch mispredictions (which would improve
>>>>>performance for some common server code).
>>>>
>>>>VIA C3: 16 pipeline stages (20W @ 1.3GHz).
>>>>Itanium2: 8 pipeline stages (62W @ 1.3GHz)
>>>
>>>PPC7447A: 7 pipeline stages (18.3W @ 1.3GHz)
>>>
>>>(You are talking "typical" power?)
>>
>>
>> No, I gave worst case power numbers for Itanium2 and VIA.
>> See http://www.via.com.tw/en/products/processors/c3/ and
>> http://www.intel.com/design/itanium/itanium/Itanium2ProdBrief.pdf.
>
> I don't see where in that marketing brochure it says the itanium
> numbers are "worst case."
"Overview
.... the Low Voltage Intel Itanium2 Processor 1.30GHz with 3MB
L3 cache offers a cost-effective solution. Just 62 watts at maximum
power consumption per processor ..."
You can find power consumption for different Itanium flavours at
http://www.intel.com/products/server/processors/server/itanium2/
Thanks,
Eugene
>>
>> Thanks,
>> Eugene
>>
>>
>>>The C3 pipeline length is unusual. What is the fetch-execute latency?
>>>Sometimes pipeline lengths are inflated by counting cache access.
>>>
>>>--
>>>Mvh./Regards, Niels Jørgen Kruse, Vanløse, Denmark
>>
>>
>>
>
>
> --
> The e-mail address in our reply-to line is reversed in an attempt to
> minimize spam. Our true address is of the form che...@prodigy.net.
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