 | | From: | Paul A. Clayton | | Subject: | Performance from process tech.? | | Date: | 12 Jan 2005 12:56:21 GMT |
|
|
 | Figures are sometimes given for the fraction of performance
improvements that come from improvements in process technology,
but how are these values computed? In particular, what baseline
is used to compare 'process-only' with real implementations? (My
guess is that transistor switching speed is used, ignoring real
constraints that designers must overcome and the benefit of
effectively doubling area with each generation.)
ISTM that several different baselines could be reasonable. One
could use a simply scaled design. This would make apparent the
benefit from small but significant effort in real instances of
design scaling, but seems unfair in not only ignoring the
effective area doubling but also the 'normal' effort of a
from-scratch design effort targeting that process.
Alternately one could use an intelligently scaled design
(weakly simulating a from-scratch effort of equal complexity).
This has the advantage of having real data points for single
process transitions (and the increase in cache size usually
associated with such transitions could be considered part of the
effective area increase advantage offered by the transition).
One could simulate a design of similar complexity (estimated as
years*(persons**0.5) [accounting for an O(p**2) communication
burden]) but twice the transistor count. This has the problem of
tending to simplify the design at each transition to use up the
additional area with the same design effort.
None of these account for the increase in actual die size brought
with improvements in process technology (in particular increases
in wafer size) nor for the increase in production volume brought
by higher performance/price nor for the disproportionately
greater price of higher performance in the market at a given
time.
Paul A. Clayton
(a 'Dysthymicdolt' reachable at aol.com)
|
|
| | From: | del cecchi | | Subject: | Re: Performance from process tech.? | | Date: | Wed, 12 Jan 2005 21:59:46 -0600 |
|
|
|
"Paul A. Clayton" wrote in message
news:20050112075621.16603.00000006@mb-m16.aol.com...
> Figures are sometimes given for the fraction of performance
> improvements that come from improvements in process technology,
> but how are these values computed? In particular, what baseline
> is used to compare 'process-only' with real implementations? (My
> guess is that transistor switching speed is used, ignoring real
> constraints that designers must overcome and the benefit of
> effectively doubling area with each generation.)
The way you do the comparison depends to some extent on why you want to
know and what you will do with the resulting data.
(gratuitous reference to American Media deleted)
One could consider something like FO4, which is the delay of a gate
(inverter? I don't remember) driving a fanout of 4 other identical
gates. No wire. One could take a "critical path" from a current design
and scale or not scale the dimensions including wire length.
>
> ISTM that several different baselines could be reasonable. One
> could use a simply scaled design. This would make apparent the
> benefit from small but significant effort in real instances of
> design scaling, but seems unfair in not only ignoring the
> effective area doubling but also the 'normal' effort of a
> from-scratch design effort targeting that process.
>
> Alternately one could use an intelligently scaled design
> (weakly simulating a from-scratch effort of equal complexity).
> This has the advantage of having real data points for single
> process transitions (and the increase in cache size usually
> associated with such transitions could be considered part of the
> effective area increase advantage offered by the transition).
>
> One could simulate a design of similar complexity (estimated as
> years*(persons**0.5) [accounting for an O(p**2) communication
> burden]) but twice the transistor count. This has the problem of
> tending to simplify the design at each transition to use up the
> additional area with the same design effort.
>
> None of these account for the increase in actual die size brought
> with improvements in process technology (in particular increases
> in wafer size) nor for the increase in production volume brought
> by higher performance/price nor for the disproportionately
> greater price of higher performance in the market at a given
> time.
>
>
> Paul A. Clayton
> (a 'Dysthymicdolt' reachable at aol.com)
Total chip performance estimates due to new process capabilities with
associated higher frequencies and larger arrays or additional
architectural features is another kettle of fish. Normally in my
experience done by a totally different group. Sort of the difference
between "how many megahertz" and "how many TPC-C"
del cecchi
>
|
|
| | From: | Paul A. Clayton | | Subject: | Re: Performance from process tech.? | | Date: | 14 Jan 2005 15:05:15 GMT |
|
|
| In article <34m9vlF4clq3tU1@individual.net>,
"del cecchi" wrote:
>The way you do the comparison depends to some extent on why you want to
>know and what you will do with the resulting data.
>(gratuitous reference to American Media deleted)
To generate a factoid for the process engineers to boast over
the circuit designers (as well as compiler writers and algorithm
developers)?
Such a figure might have a minor use for estimating future
trends, but it seems to mostly be a curiosity.
|
|
| | From: | Del Cecchi | | Subject: | Re: Performance from process tech.? | | Date: | Fri, 14 Jan 2005 11:00:19 -0600 |
|
|
| Paul A. Clayton wrote:
> In article <34m9vlF4clq3tU1@individual.net>,
> "del cecchi" wrote:
>
>
>>The way you do the comparison depends to some extent on why you want to
>>know and what you will do with the resulting data.
>>(gratuitous reference to American Media deleted)
>
>
> To generate a factoid for the process engineers to boast over
> the circuit designers (as well as compiler writers and algorithm
> developers)?
>
> Such a figure might have a minor use for estimating future
> trends, but it seems to mostly be a curiosity.
>
>
>
Then use unloaded inverter delay. Hot damn, 10 picoseconds.
|
|
